This invention relates to dual-gain phase-locked loop circuitry and delay-locked loop circuitry with reduced jitter, and particularly to such circuitry for use in a programmable logic device.
It is known to incorporate phase-locked loop (“PLL”) circuitry or delay-locked loop (“DLL”) circuitry on programmable logic devices (“PLDs”). For example, it has become common for PLDs to accommodate various input/output standards, some of which require very accurate high-speed clocks. One way of providing such clocks is to provide PLL or DLL circuitry on the PLD. For convenience, PLLs and DLLs will be referred to collectively herein as “loop circuits” where appropriate.
A basic PLL includes a phase-frequency detector (“PFD”), a charge pump, a loop filter and a voltage-controlled oscillator (“VCO”), connected in series. The input or reference frequency is one input to the PFD. The output of the VCO, which is the output of the PLL, is also fed back to another input of the PFD. If the feedback signal is not locked to the input reference signal, then the PFD output will be a signal (voltage) whose sign is indicative of whether the output leads or lags and whose magnitude is indicative of the amount of lead or lag. That signal is filtered by the charge pump and loop filter and is input to the VCO, causing the output frequency to change. Eventually, the output signal will lock to the phase of the input reference signal. In this simple example, the output signal also will lock to the frequency of the input reference signal, but in most PLLs, counters on the input and output of the PLL are used to divide the input frequency, while a counter/divider in the feedback loop is used to multiply the input frequency. Thus the frequency of the output signal can be any rational multiple of the input frequency, but will be phase-locked to the input frequency.
However, the VCO typically has a substantial voltage gain, which can be correlated to the frequency range over which it is to operate. As a result, slight variations in the input and feedback signals, resulting from process, temperature and supply variations or other sources of noise, can be greatly magnified by the PLL, resulting in an output signal variation known as “jitter.”
For example, for a PLL constructed using 90 nm integrated circuit technology, for which the minimum expected frequency isfmin=300 MHz,the maximum expected frequency isfmax=1000 MHz,the supply voltage isVcc=1.2 V, andthe device saturation voltage isVDSsat=0.2 V,the VCO gain, KVCO, can be estimated as                               K          VCO                =                ⁢                              (                                          f                max                            -                              f                min                                      )                    /                      (                                          V                cc                            -                              2                ⁢                                  V                  DSsat                                                      )                                                  =                ⁢                              (                          1000              -              300                        )                    /                      (                          1.2              -              0.4                        )                                                  =                ⁢                  875          ⁢                                          ⁢          MHz          ⁢                      /                    ⁢                      V            .                              Thus, even a 1 mV variation in the input signal can give rise to an output frequency variation of almost 1 MHz. Insofar as the voltages involved are almost always in generally the same range, the gain is effectively a function of the desired operating range, which is determined by the particular application.
The situation is similar for a DLL. A basic DLL includes a phase detector (“PD”), a charge pump, a loop filter and a voltage-controlled delay line (“VCDL”), connected in series. The input or reference signal is one input to the PD. An output of the VCDL is also fed back to another input of the PD. If the phase of the feedback signal is not locked to that of the input reference signal, then the PD output will be a signal (voltage) whose sign is indicative of whether the output leads or lags and whose magnitude is indicative of the amount of lead or lag. That signal is filtered by the charge pump and loop filter and is input to the VCDL, delaying the output and causing its phase to change. Eventually, the output signal will lock to the phase of the input reference signal. Unlike PLLs, DLLs do not affect the frequency of the signal; the output frequency will automatically match the input frequency.
However, like a VCO, a VCDL may have a substantial voltage gain. Thus, as with a PLL, slight variations in the input and feedback signals, resulting from process, temperature and supply variations or other sources of noise, can be greatly magnified by the DLL, resulting in output signal jitter.
It would be desirable to be able to reduce the jitter of a loop circuit without regard to its operating range. It would be particularly desirable to be able to control the jitter in a programmable way.